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INTEGRATED CIRCUITS
SCN68562 Dual universal serial communications controller (DUSCC)
Product specification IC19 Data Handbook 1995 May 01
Philips Semiconductors
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
DESCRIPTION
The Philips Semiconductors SCN68562 Dual Universal Serial Communications Controller (DUSCC) is a single-chip MOS-LSI communications device that provides two independent, multi-protocol, full-duplex receiver/transmitter channels in a single package. It supports bit-oriented and character-oriented (byte count and byte control) synchronous data link controls as well as asynchronous protocols. The SCN68562 interfaces to the 68000 MPUs via asynchronous bus control signals and is capable of program-polled, interrupt driven, block-move or DMA data transfers. The operating mode and data format of each channel can be programmed independently. Each channel consists of a receiver, a transmitter, a 16-bit multifunction counter/timer, a digital phase-locked loop (DPLL), a parity/CRC generator and checker, and associated control circuits. The two channels share a common bit rate generator (BRG), operating directly from a crystal or an external clock, which provides 16 common bit rates simultaneously. The operating rate for the receiver and transmitter of each channel can be independently selected from the BRG, the DPLL, the counter/timer, or from an external 1X or 16X clock, making the DUSCC well suited for dual-speed channel applications. Data rates up to 4Mbits per second are supported.
The transmitter and receiver each contain a four-deep FIFO with appended transmitter command and receiver status bits and a shift register. This permits reading and writing of up to four characters at a time, minimizing the potential of receiver overrun or transmitter underrun, and reducing interrupt or DMA overhead. In addition, a flow control capability is provided to disable a remote transmitter when the FIFO of the local receiving device is full. Two modem control inputs (DCD and CTS) and three modem control outputs are provided. These inputs and outputs can be optionally programmed for other functions.
FEATURES General Features
transmitter
* Dual full-duplex synchronous/asynchronous receiver and * Multiprotocol operation
- BOP: HDLC/ADCCP, SDLC, SDLC loop, X.25 or X.75 link level, etc. - COP: BISYNC, DDCMP - ASYNC: 5-8 bits plus optional parity
* Four character receiver and transmitter FIFOs
A PACKAGE
7 8 1 47 46
PIN CONFIGURATIONS
N PACKAGE
IACKN A3 A2 A1 RTxDAKBN/ GPI1BN IRQN RESETN RTSBN/ SYNOUTBN TRxCB 1 2 3 4 5 6 7 8 9 48 VDD 47 46 45 44 43 42 41 40 39 DIP 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A4 A5 A6 RTxDAKAN/ GPI1AN X1/CLK X2/IDCN RTSAN/ SYNOUTAN TRxCA RTxCA DCDAN/ SYNIAN Rxda TxDA TxDAKAN/ GPI2AN RTxDRQAN/ GPO1AN TxDRQAN/ GPO2AN/RTSAN CTSAN/LCAN D0 D1 D2 D3 DONEN R/WN CSN 20 21 Pin Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 33 TOP VIEW Pin Function 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 CSN R/WN DONEN D3 D2 D1 D0 NC CTSAN/LCAN TxDRQAN/ GPO2AN/RTSAN RTxDRQAN/ GPO1AN TxDAKAN/ GPI2AN TxDA RxDA NC DCDAN/ SYNIAN RTxCA TRxCA RTSAN/ SYNOUTAN X2/IDCN X1/CLK RTxDAKAN/ GPI1AN A6 A5 A4 VDD 34 PLCC INDEX CORNER
RTxCB 10 DCDBN/ 11 SYNIBN RxDB 12 TxDB 13 TxDAKBN/ GPI2BN RTxDRQBN/ GPO1BN TxDRQBN/ GPO2BN/RTSBN CTSBN/LCBN 14 15 16 17
D7 18 D6 19 D5 20 D4 21 DTACKN 22 DTCN 23 GND 24
IACKN A3 A2 A1 RTxDAKBN/ GPI1BN IRQN NC RESETN RTSBN/ SYNOUTBN TRxCB RTxCB DCDBN/ SYNIBN NC RxDB TxDB TxDAKBN/ GPI2BN RTxDRQBN/ GPO1BN TxDRQBN/ GPO2BN/RTSBN CTSBN/LCBN D7 D6 D5 D4 DTACKN DTCN GND
SD00222
Figure 1. Pin Configurations
1995 May 01
2
853-0831 15179
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
* 0 to 4MHz data rate * Programmable bit rate for each receiver and transmitter selectable
from: - 16 fixed rates: 50 to 38.4k baud - One user-defined rate derived from programmable counter/timer - External 1X or 16X clock - Digital phase-locked loop
* Break generation with handshake for counting break characters * Detection of start and end of received break * Character compare with optional interrupt on match * Transmits up to 4Mbs and receive up to 2Mbps data rates
Character-Oriented Protocol Features
* Parity and FCS (frame check sequence LRC or CRC) generation
and checking
* Programmable data encoding/decoding: NRZ, NRZI, FM0, FM1,
Manchester
* Programmable channel mode: full- and half-duplex, auto-echo, or
local loopback
* Programmable data transfer mode: polled, interrupt, DMA, wait * DMA interface
- Compatible with the Philips Semiconductors SCB68430 Direct Memory Access Interface (DMAI) and other DMA controllers - Single- or dual-address dual transfers - Half- or full-duplex operation - Automatic frame termination on counter/timer terminal count or DMA DONE
* Character length: 5 to 8 bits * Odd or even parity, no parity, or force parity * LRC or CRC generation and checking * Optional opening PAD transmission * One or two SYN characters * External sync capability * SYN detection and optional stripping * SYN or MARK line-fill on underrun * Idle in MARK or SYNs * Parity, FCS, overrun, and underrun error detection
BISYNC Features
- EBCDIC or ASCII header, text and control messages - SYN, DLE stripping - EOM (end of message) detection and transmission - Auto transparent mode switching - Auto hunt after receipt of EOM sequence (with closing PAD check after EOT or NAK) - Control character sequence detection for both transparent and normal text
* Interrupt capabilities
- Daisy chain option - Vector output (fixed or modified by status) - Programmable internal priorities - Maskable interrupt conditions
* Multi-function programmable 16-bit counter/timer
- Bit rate generator - Event counter - Count received or transmitted characters - Delay generator - Automatic bit length measurement
Bit-Oriented Protocol Features
* Modem controls
- RTS, CTS, DCD, and up to four general I/O pins per channel - CTS and DCD programmable autoenables for Tx and Rx - Programmable interrupt on change of CTS or DCD
* Character length: 5 to 8 bits * Detection and transmission of residual character: 0-7 bits * Automatic switch to programmed character length for 1 field * Zero insertion and deletion * Optional opening PAD transmission * Detection and generation of FLAG, ABORT, and IDLE bit patterns * Detection and generation of shared (single) FLAG between
frames
* On-chip oscillator for crystal * TTL compatible * Single +5V power supply
Asynchronous Mode Features
* Character length: 5 to 8 bits * Odd or even parity, no parity, or force parity * Up to two stop bits programmable in 1/16-bit increments * 1X or 16X Rx and Tx clock factors * Parity, overrun, and framing error detection * False start bit detection * Start bit search 1/2-bit time after framing error detection
1995 May 01 3
* Detection of overlapping (shared zero) FLAGs * ABORT, ABORT-FLAGs, or FCS FLAGs line-fill on underrun * Idle in MARK or FLAGs * Secondary address recognition including group and global
address
* Single- or dual-octet secondary address * Extended address and control fields * Short frame rejection for receiver * Detection and notification of received end of message * CRC generation and checking * SDLC loop mode capability
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
ORDERING INFORMATION
DESCRIPTION 48-Pin Plastic Dual In-Line Package (DIP) 52-Pin Plastic Leaded Chip Carrier (PLCC) Package VCC = +5V +5%, TA = 0C to +70C Serial Data Rate = 4Mbps Maximum SCN68562C4N48 SCN68562C4A52 DWG # SOT240-1 SOT238-3
NOTE: See SCN26562/SCN68562 User's Guide for detailed description of all the features.
BLOCK DIAGRAM
D0-D7 BUS BUFFER CHANNEL MODE AND TIMING A/B DPLL CLK MUX A/B INTERFACE/ OPERATION CONTROL ADDRESS DECODE DTACKN RWN A1-A6 CSN RESETN MPU INTERFACE COUNTER/ TIMER A/B R/W DECODE DMA CONTROL CCRA/B RTxDRQAN/GPO1AN RTxDRQBN/GPO1BN TxDRQAN/GPO2AN TxDRQBN/GPO2BN RTxDAKAN/GPI1AN RTxDAKBN/GPI1BN TxDAKAN/GPI2AN TxDAKBN/GPI2BN DTCN DONEN PCRA/B RSRA/B TRSRA/B ICTSRA/B DMA INTERFACE GSR CMR1A/B CMR2A/B OMRA/B INTERNAL BUS C/T CLK MUX A/B CTCRA/B CTPRHA/B CTPRLA/B CTHA/B CTLA/B DPLL A/B BRG
TRANSMIT A/B TRANS CLK MUX TPRA/B TTRA/B TX SHIFT REG TRANSMIT 4 DEEP FIFO TxD A/B
TRxCA/B RTxCA/B RTSBN/SYNOUTBN RTSAN/SYNOUTAN CTSA/BN DCDBN/SYNIBN DCDAN/SYNIAN SPECIAL FUNCTION PINS
CONTROL
CRC GEN SPEC CHAR GEN LOGIC
RECEIVER A/B RCVR CLK MUX INTERRRUPT CONTROL ICRA/B IRQN IERA/B IACKN IVR IVRM DUSCC LOGIC RPRA/B RTRA/B S1RA/B S2RA/B RxD A/B RCVR SHIFT REG RECEIVER 4 DEEP FIFO CRC ACCUM BISYNC COMPARE LOGIC
X1/CLK X2/IDCN
OSCILLATOR
SD00223
Figure 2. Block Diagram
1995 May 01
4
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
PIN DESCRIPTION
In this data sheet, signals are discussed using the terms `active' and `inactive' or `asserted' and `negated' independent of whether the signal is active in the High (logic 1) or Low (logic 0) state. N at the end of a pin name signifies the signal associated with the pin is active-Low (see individual pin description for the definition of the active level of each signal.) Pins which are provided for both channels are designated by A/B after the name of the pin and the active-Low state indicator, N, if applicable. A similar method is used for registers provided for both channels: these are designated by either an underline or by A/B after the name. MNEMONIC A1 - A6 D0 - D7 DIP PIN NO. 4-2, 45-47 31-28, 21-18 TYPE I I/O NAME AND FUNCTION Address Lines: Active-High. Address inputs which specify which of the internal registers is accessed for read/write operation. Bidirectional Data Bus: Active High, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All data, command, and status transfers between the CPU and the DUSCC take place over this bus. The data bus is enabled when CSN is Low, during interrupt acknowledge cycles and single-address DMA acknowledge cycles. Read/Write: A High input indicates a read cycle and a Low input indicates a write cycle when a cycle is initiated by assertion of the CSN input. Chip Select: Active-Low input. When Low, data transfers between the CPU and the DUSCC are enabled on D0 - D7 as controlled by the R/WN and A1 - A6 inputs. When CSN is High, the DUSCC is isolated from the data bus (except during interrupt acknowledge cycles and single-address DMA transfers) and D0 - D7 are placed in the 3-State condition. Data Transfer Acknowledge: Active-Low, 3-State. DTACKN is asserted on a write cycle to indicate that the data on the bus has been latched, and on a read cycle or interrupt acknowledge cycle to indicate valid data is on the bus. The signal is negated when completion of the cycle is indicated by negation of the CSN or IACKN input, and returns to the inactive state (3-State) a short period after it is negated. In a single address DMA mode, data is latched with the falling edge of DTCN. DTACKN is negated when completion of the cycle is indicated by the assertion of DTCN or negation of DMA acknowledge inputs (whichever occurs first), and returns to the inactive state (3-State) a short period after it is negated. When negated, DTACKN becomes an open-drain output and requires an external pull-up resistor. Interrupt Request: Active-Low, open-drain. This output is asserted upon occurrence of any enabled interrupting condition. The CPU can read the general status register to determine the interrupting condition(s), or can respond with an interrupt acknowledge cycle to cause the DUSCC to output an interrupt vector on the data bus. Interrupt Acknowledge: Active-Low. When IACKN is asserted, the DUSCC responds by placing the contents of the interrupt vector register (modified or unmodified by status) on the data bus and asserting DTACKN. If no active interrupt is pending, DTACKN is not asserted. Crystal or External Clock: When using the crystal oscillator, the crystal is connected between pins X1 and X2. If a crystal is not used, and external clock is supplied at this input. This clock is used to drive the internal bit rate generator, as an optional input to the counter/timer or DPLL, and to provide other required clocking signals. Crystal or Interrupt Daisy Chain: When a crystal is used as the timing source, the crystal is connected between pins X1 and X2. This pin can be programmed to provide and interrupt daisy chain active-Low output which propagates the IACKN signal to lower priority devices, if no active interrupt is pending. This pin should be grounded when an external clock is used on X1 and X2, is not used as an interrupt daisy chain output. Master Reset: Active-Low. A low on this pin resets the transmitters and receivers and resets the registers shown in Table 1 of the CDUSCC Users' Guide. Reset in asynchronous, i.e., no clock is required. Channel A (B) Receiver Serial Data Input: The least significant bit is received first. If external receiver clock is specified for the channel, the input is sampled on the rising edge of the clock. Channel A (B) Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held in the marking (High) condition when the transmitter is disabled or when the channel is operating in local loopback mode. If external transmitter clock is specified for the channel, the data is shifted on the falling edge of the clock. Channel A (B) Receiver/Transmitter Clock: As an input, it can be programmed to supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, can supply the counter/timer output, the transmitter shift clock (1X), or the receiver sampling clock (1X). The maximum external receiver/transmitter clock frequency is 4MHz.
R/WN CSN
26 25
I I
DTACKN
22
O
IRQN
6
O
IACKN
1
I
X1/CLK
43
I
X2/IDCN
42
O
RESETN
7
I
RxDA, RxDB
37, 12
I
TxDA, TxDB
36, 13
O
RTxCA, RTxCB
39, 10
I/O
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Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
PIN DESCRIPTION (Continued)
MNEMONIC TRxCA, TRxCB DIP PIN NO. 40, 9 TYPE I/O NAME AND FUNCTION Channel A (B) Transmitter/Receiver Clock: As an input, it can supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer output, the DPLL output, the transmitter shift clock (1X), the receiver sampling clock (1X), the transmitter BRG clock (16X), The receiver BRG clock (16X), or the internal system clock (X1/2). The maximum external receiver/transmitter clock frequency is 4MHz. Channel A (B) Clear-To-Send Input or Loop Control Output: Active-Low. The signal can be programmed to act as an enable for the transmitter when not in loop mode. The DUSCC detects logic level transitions on this input and can be programmed to generate an interrupt when a transition occurs. When operating in the COP loop mode, this pin becomes a loop control output which is asserted and negated by DUSCC commands. This output provides the means of controlling external loop interface hardware to go on-line and off-line without disturbing operation of the loop. Channel A (B) Data Carrier Detected or External Sync Input: The function of this pin is programmable. As a DCD active-Low input, it acts as an enable for the receiver or can be used as a general purpose input for the DCD function, the DUSCC detects logic level transitions on this input and can be programmed to generate an interrupt when a transition occurs. As an active-Low external sync input, it is used in COP modes to obtain character synchronization without receipt of a SYN character. This mode can be used in disc or tape controller applications or for the optional byte timing lead in X.21. Channel A (B) Receiver/Transmitter DMA Service Request or General Purpose Output: Active-Low. For half-duplex DMA operation, this output indicates to the DMA controller that one or more characters are available in the receiver FIFO (when the receiver is enabled) or that the transmit FIFO is not full (when the transmitter is enabled). For full-duplex DMA operation, this output indicates to the DMA controller that data is available in the receiver FIFO. In non-DMA mode, this pin is a general purpose output that can be asserted and negated under program control. Channel A (B) Transmitter DMA Service Request, General Purpose Output, or Request-to-Send: Active-Low. For full-duplex DMA operation, this output indicates to the DMA controller that the transmit FIFO is not full and can accept more data. When not in full-duplex DMA mode, this pin can be programmed as a general purpose or a Request-to -Send output, which can be asserted and negated under program control (see Detailed Operation). Channel A (B) Receiver/Transmitter DMA Acknowledge or General Purpose Input: Active-Low. For half-duplex single address DMA operation, this input indicates to the DUSCC that the DMA controller has acquired the bus and that the requested bus cycle (read receiver FIFO or load transmitter FIFO) is beginning. For full-duplex single address DMA operation, this input indicates to the DUSCC that the DMA controller has acquired the bus and that the requested read receiver FIFO bus cycle is beginning. Because the state of this input can be read under program control, it can be used as a general purpose input when not in single address DMA mode. Channel A (B) Transmitter DMA Acknowledge or General Purpose Input: Active-Low. When the channel is programmed for full-duplex single address DMA operation, this input is asserted to indicate to the DUSCC that the DMA controller has acquired the bus and that the requested load transmitter FIFO bus cycle is beginning. Because the state of this input can be read under program control, it can be used as a general purpose input when not in full-duplex single address DMA mode. Device Transfer Complete: Active-Low. DTCN is asserted by the DMA controller to indicate that the requested data transfer is complete. Done: Active-Low, open-drain. See Detailed Operation for a description of the function of this pin. Channel A (B) Sync Detect or Request-to-Send: Active-Low. If programmed as a sync output, it is asserted one bit time after the specified sync character (COP or BISYNC modes) or a FLAG (BOP modes) is detected by the receiver. As a Request-to-Send modem control signal, it functions as described previously for the TxDRQN/RTSN pin. +5V + 10% power input. Signal and power ground input.
CTSA/BN, LCA/BN
32, 17
I/O
DCDA/BN, SYNIA/BN
38, 11
I
RTxDRQA/BN, GPO1A/BN
34, 15
O
TxDRQA/BN, GPO2A/BN, RTSA/BN
33, 16
O
RTxDAKA/BN, GPI1A/BN
44, 5
I
TxDAKA/BN, GP12A/BN
35, 14
I
DTCN DONEN RTSA/BN, SYNOUTA/BN
23 27 41, 8
I I/O O
VDD GND
48 24
I I
1995 May 01
6
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
ABSOLUTE MAXIMUM RATINGS1
SYMBOL TA TSTG VCC Storage Temperature Voltage from VCC to GND3 ground3 PARAMETER Operating ambient temperature2 RATING 0 to +70 -65 to +150 -0.5 to +7.0 UNIT C C V
VS Voltage from any pin to -0.5 to VCC +0.5 V NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation section of this specification is not implied. 2. For operating at elevated temperatures, the device must be derated based on +150C maximum junction temperature and thermal resistance of 40C/W for plastic DIP and 42C/W for PLCC. 3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
DC ELECTRICAL CHARACTERISTICS1, 4
TA = 0 to +70C, VCC = 5.0V + 5% SYMBOL VIL PARAMETER Input low voltage: All except X1/CLK X1/CLK Input high voltage: All except X1/CLK X1/CLK Output low voltage: All except IRQN, DONEN IRQN, DONEN Output high voltage: (Except open drain outputs) X1/CLK input low current3 X1/CLK input high current3 X2 input low current3 X2 input high current3 Input low current DTCN, TxDAKA/BN, RTxDAKA/BN Input leakage current Output off current high, 3-State data bus Output off current low, 3-State data bus Open drain output low current in off state: DONEN IRQN, DTACKN Open drain output high current in off state: DONEN, IRQN, DTACKN Power supply current IOL = 5.3mA IOL = 8.8mA IOH = -400A VIN = 0, X2 = GND VIN = VCC, X2 = GND VIN = 0, X1 = open VIN = VCC, X1 = open VIN = 0 VIN = 0 to VCC VIN = VCC VIN = 0 VIN = 0 -120 -5 VIN = VCC 5 VO = 0 to VCC 275 10 15 20 -25 2.4 -5.5 -100 100 -40 -5 -5 5 5 0.0 1.0 TEST CONDITIONS LIMITS Min Typ Max 0.8 0.4 2.0 2.4 UNIT
V V V V V V V mA mA A A A A A A A A A mA pF pF pF
VIH
VCC 0.5 0.5
VOL
VOH IILX1 IIHX1 IILX2 IIHX2 IIL IL IOZH IOZL IODL
IODH ICC
CIN Input capacitance2 VCC = GND = 0 COUT Output capacitance2 VCC = GND = 0 CI/O Input/output capacitance2 VCC = GND = 0 NOTES: 1. Parameters are valid over specified temperature and voltage range. 2. These values were not explicitly tested; they are guaranteed by design and characterization data. 3. X1/CLK and X2 are not tested with a crystal installed. 4. This specification applies to revision D, revision E and later revisions.
1995 May 01
7
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
AC ELECTRICAL CHARACTERISTICS1, 2, 3, 4
NO NO. 1 2 3 4 5 6 7 7A 8 9 10 11 12 12A 13 14 15 16 17 18 19 FIGURE 3 4,6 4,6 4,6 4,6 4,6 4,5 5 4,5 4 6 4,6 4,6 6 4,6 4,6 5 8 8 8 9
TA = -55 to +110c, VCC = 5V + 10% Min 1.2 10 0 0 0 160 30 LIMITS Typ Max UNIT S nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS MHz nS MHz nS MHz nS MHz nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS
PARAMETER RESETN pulse width A1 - A6 set-up time to CSN Low A1 - A6 hold time from CSN High RWN set-up time to CSN Low RWN hold time to CSN High CSN High pulse width4 CSN or IACKN High from DTACKN Low IACKN High to DTACKN High Data valid from CSN or IACKN Low Data bus floating from CSN High7 Data hold time from DTACKN Low5 DTACKN Low from read data ready DTACKN Low from CSN Low CSN Low to write data valid DTACKN High from CSN High DTACKN high impedance from CSN High DTACKN Low from IACKN Low GPI input set-up time to CSN Low GPI input hold time from CSN Low GPO output valid from DTACKN Low IRQN High from: Read RxFIFO (RxRDY interrupt) Write TxFIFO (TxRDY interrupt)8 Write RSR (Rx condition interrupt)8 Write TRSR (Rx/Tx interrupt)8 Write ICTSR (port change and CT int.)8 X1/CLK High or Low time X1/CLK frequency CTCLK High or Low time CTCLK frequency RxC High or Low time RxC frequency (16X or 1X)9 TxC High or Low time TxC frequency (16X or 1X) TxD output from TxC input Low (1X) (16X) TxD output from TxC output Low RxD data set-up time to RxC High RxD data hold time from RxC High IACKN Low to daisy chain Low Data valid from receive DMA ACKN DTCN width RDYN Low to DTCN Low Data bus float from DTCN Low7 DMA ACKN Low to RDYN (DTACKN) Low RDYN High from DTCN Low RDYN High impedance from DTCN Low Receive DMA REQN High from DMA ACKN Low Receive DMA ACKN width Receive DMA ACKN Low to DONEN Low Data set-up to DTCN Low Data hold from DTCN Low6 Transmit DMA REQN High from ACKN Low Transmit DMA ACKN width Transmit DMA ACKN Low to DONEN Low output DTCN Low DONEN output High CSN Low to transmit DONEN Low output 8
200 300 100 0 0 560 50 150 185 550 20 100 300 450 450 400 400 400 25 2.0 100 0 110 0 110 0 14.7456 16 4 4 4 240 435 50
20
10
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 40A 41 1995 May 01
11 11 12 12 13 15 14,15 14,15 15 14,15 14,15 14,15 15 15 14,15 14 14 14 14 14 14 16
50 50 200 300 100 80 200 360 230 250 325 150 250 50 50 340 150 250 260 300
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
NO.
FIGURE
PARAMETER
Min
LIMITS Typ
42 16 CSN Low to transmit DMA REQ negated nS 43 16 CSN Low to receive DONEN Low nS 44 16 CSN Low to receive DMA REQ negated nS NOTES: 1. Parameters are valid over specified temperature range. 2. All voltage measurements are referenced to ground (GND). For DC and functional testing, all inputs except X1/CLK swing between 0.8V and 2.0V with a transition time of 20ns maximum. For X1/CLK, this swing is between 0.4V and 2.4V All time measurements are referenced at input voltages of 0.4V and 2.4V for all inputs. Output levels are referenced at 1.2V and 2.0V, as appropriate. 3. Test conditions for outputs: CL = 150pF, except open-drain outputs. Test condition for open-drain outputs: CL = 50pF to GND, RL = 2.7k to VCC except DTACKN whose RL = 820 to VCC and CL = 150pF to GND and DONEN which requires CL = 50pF to GND and RL = 1k to VCC. 4. This specification will impose maximum 68000 CPU CLK to 6MHz. Higher CPU CLK can be used if repeating bus cycles are not performed. 5. Execution of the valid command (after it is latched) requires three falling edges of X1 (see Figure 14). 6. In single address DMA mode write operation, data is latched by the falling edge of DTCN. 7. These values were not explicitly tested, they are guaranteed by design and characterization data. 8. These timings are from the falling edge of DTACKN (not CSN rising). 9. X1/CLK frequency must be at least four times the receiver serial data rate.
RESETN
Max 400 300 400
UNIT
1
SD00224
Figure 3. Reset Timing
2 A1-A6 4 5 3
R/WN 6 CSN 9
8 D0-D7
11 DTACKN
7
13 12 14
SD00225
Figure 4. Bus Timing (Read Cycle)
X1/CLK
DTACKN
COMMAND VALID
SD00226
Figure 5. Command Timing 1995 May 01 9
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
2 A1-A6 5 4 RWN 12 CSN 6
3
12A D0-D7 10
DTACKN
7 13 14
SD00228
Figure 6. Bus Timing (Write Cycle)
IRQN
15 IACKN 8 D0-D7 11 7 7A
DTACKN
SD00229
Figure 7. Interrupt Cycle Timing
1995 May 01
10
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
RWN
CSN 16 17 GPI1N AND/OR GPI2N
RWN
CSN 18 GPO1N AND/OR GPO2N OLD DATA NEW DATA
DTACK
SD00230
Figure 8. Port Timing
CSN VM 19 VOL +0.5V IRQN VOL
SD00231
Figure 9. Interrupt Timing
+5V C1 = C2: 0-5pF + (STRAY < 5pF) DRIVING FROM EXTERNAL SOURCE +5V 20 X1/CLK CTCLK RxC TxC 20 C2 X2 X2 14.7456 MHz CRYSTAL SERIES RESISTANCE3 SHOULD BE LESS THAN 180 470 X1 C1 DUSCC X1 1K CLOCK TO OTHER CHIPS
SD00232
Figure 10. Clock Timing
1995 May 01
11
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
1 BIT TIME (1 OR 16 CLOCKS) TxC (INPUT) 21
TxD
22 TxC (1X OUTPUT)
SD00227
Figure 11. Transmit Timing
SYNOUT
SYNIN
RxC (1x) INPUT 23 24
RxD
SD00233
Figure 12. Receive Timing
IACKN 25
IDCN
SD00234
Figure 13. Interrupt Daisy Chain Timing
1995 May 01
12
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
39 TxDAKN 30
36 D0-D7
37
32 RDYN (DTACKN) 31 DTCN 28 DONEN (INPUT) 27
TxDRQN 38 DONEN (OUTPUT) 40 40A
SD000235
Figure 14. DMA Transmit Write Timing--Single Address DMA Mode
34 RTxDAKN 26 D0-D7 30 RDYN (DTACKN) 31 DTCN 28 DONEN (OUTPUT) 35 27 40A 32 29
RTxDRQN 33
SD00236
Figure 15. DMA Receive Read Timing--Single Address DMA Mode
1995 May 01
13
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
DONEN (OUTPUT) 41 CSN
DTACKN
DONEN (INPUT)
42 TxDRQN
TRANSMIT DUAL ADDRESS DMA MODE 43 DONEN (OUTPUT) (EOM) 44 RTxDRQN
SD00237
Figure 16. Dual Address DMA Mode Timing
1995 May 01
14
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
DIP48: plastic dual in-line package; 48 leads (600 mil)
SOT240-1
1995 May 01
15
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
PLCC52: plastic leaded chip carrier; 52 leads; pedestal
SOT238-3
1995 May 01
16
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
NOTES
1995 May 01
17
Philips Semiconductors
Product specification
Dual universal serial communications controller (DUSCC)
SCN68562
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 2000 All rights reserved. Printed in U.S.A. Date of release: 01-00 Document order number: 9397 750 06825
Philips Semiconductors
1995 May 01 18

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